1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device. More particularly, the present invention relates to a nonvolatile semiconductor memory device having memory cells of field effect transistor type.
2. Description of the Related Art
In a flash memory, erasure is collectively performed on a group of memory cells included in one sector. However, due to a variation in the erasure characteristic of the memory cell group included in the sector, there may be a memory cell or cells (digit lines) the threshold voltage (hereinafter referenced as “Vtm”) of which is 0 V or lower or through which an offset current flows (i.e., the memory cells go to a depletion level) when attention is paid to any single digit line, as the result of erasing operation. Then, when the next write cycle is executed using a channel hot electron (CHE) method, a predetermined write potential is applied to the drains of the memory cell group. At this point, even if a memory cell or a digit line at a depletion level is nonselected (i.e., a control gate potential equals a ground level), an off-leakage current flows through the memory cell. If the off-leakage current flows from the nonselected memory cell to the bit line, a sufficient write current does not flow through a selected memory cell or cells to be written, thus deteriorating the write characteristic of the flash memory.
As one of measures against such problems as described above, “source bias writing” has been put in practical use. According to the source bias writing, a predetermined positive potential is applied in a write operation to a common source line connected in common to a group of memory cells. As a result, the threshold voltage Vtm rises due to a substrate effect and an off-leakage current flowing through a nonselected memory cell or cells are suppressed.
As a conventional art relating to source potential control, there are known the techniques described in National Publication of International Patent Application No. 2003-507834 and Japanese Patent Laid-Open No. 2000-276882. According to the flash memory device described in National Publication of International Patent Application No. 2003-507834, an array of resistors is connected between a common source line and a ground. At the time of writing memory cells, a resistor value is selected and the source potential rises. According to the nonvolatile semiconductor memory device described in Japanese Patent Laid-Open No. 2000-276882, a predetermined bias voltage is applied to a common source line at the time of reading memory cells.
The inventor of the present invention is the first to focus on the following. That is, when the write-erase cycle of memory cells is repeated, the threshold voltage of a memory cell or cells at a depletion level may lower further. At this point, it is possible to further increase the source potential in source bias writing in order to weaken the effect of the threshold voltage. However, if the source voltage exceeds a certain level, it is no longer possible to secure a sufficient drain-source voltage Vds at a memory cell or cells. As a result, a desired write current does not flow through the selected memory cell or cells to be written. This results in a remarkable deterioration in the write characteristic or an inability to write.